Dr. Valeriy Sukharev is the Technical Lead and Principle Engineer of the Design-to-Silicon division of Mentor Graphics Corporation. He holds Ph.D. in Physical Chemistry from the Karpov Institute of Physical Chemistry, Moscow, Russia. He leads research and development of new full-chip modeling and simulation capabilities for the semiconductor processing and DFM/DFR applications. He has authored and edited a number of books, published more than 100 papers in scientific journals and holds 20 plus U.S. patents. He has been with Mentor Graphics R&D for six years. Prior to Mentor Graphics, he was a Chief Scientists with Ponte Solutions, Inc., Mountain View, CA, Visiting Professor with Brown University, Providence, RI, and a Guest Researcher with the National Institute of Standards and Technology (NIST), Gaithersburg, MD. He held senior technical positions at LSI Logic Advanced Development Lab, Milpitas, CA.
Accurate simulation of the power map, Current densities, Temperature and IR-drop for accurate chip-scale electromigration assessment.